Wireless SoC Development
Wireless Designs have evolved from a simple layered architecture that separates Modem, MAC and higher layer algorithms to a highly complex cross layer architecture which couples higher layer algorithms and the baseband modem. In addition, massive MIMO brings about considerable challenges in creating an efficient cross layer architecture. FPGA SoC. ARM processor + FPGA fabric are well positioned to address cross layer architectural consideration in the Wireless Infrastructure space. Creating a SW-FPGA architecture partition is not trivial and requires an in-depth understanding of wireless algorithms and SoC architecture.
Symbol Level Processing (Modems, Channel Estimation, MIMO processing)
Accelerators like Matrix Multiplication / Inversion, FEC, Channel Estimation
Processor Sub System
Scheduling DMA between processor memory and FPGA accelerators
Bit Level processing, Scheduling algorithms and Higher layer protocols
Its just not about FPGA or Processor
With heterogeneous architectures evolving, it is very important to carefully architect the total solution across Processor and FPGA. Data transfer between different computing elements in an Heterogeneous architecture is key to attaining performance. Efficient device drivers and DMA play a big role in extracting the performance. Carefully designed and scheduled DMA, Device drivers and of course FPGA RTL are key elements to a high performance implementation. More important is the ability to characterize the performance post implementation and in field to ensure performance bottlenecks do not impact system throughput. A holistic view of the entire system is needed to ensure the SW and FPGA work in synergy.
The development methodology is also key to a successful Wireless SoC design. A multitude of complex skills are required to put together a Wireless SoC and an effective methodology is needed to ensure abstraction, integration and synergy.
|Algorithm Exploration||Floating Point Analysis||Implementation Vs Performance Trade Offs|
|Algorithm Analysis||Fixed Point Analysis||Performance Evaluation|
SoC Architecture and FPGA-Firmware Partition
|Accelerators and Functional Development||Verification/Validation against Algorithm model|
|Data Path Performance Analysis||FPGA Data Path and DMA Development||Timing Closure|
|Firmware||Device Tree Generation|
Preloader and Boot Sequence
|API and Application development||Data Path Performance evaluation||Functaional validation against Algorithm mode|